1. Filed of the Invention
This invention relates generally to a computer processor, and more specifically, to a packet parsing processor including a parsing engine to perform content inspection on network packets with an instruction set that provides programmable parsing operations.
2. Description of Related Art
Until recently, a lack of network bandwidth posed restraints on network performance. But emerging high bandwidth network technologies now operate at rates that expose limitations within conventional computer processors. Even high-end network devices using state of the art general purpose processors are unable to meet the demands of networks with data rates of 2.4-Gbps, 10-Gbps, 40-Gbps and higher.
Network processors are a recent attempt to address the computational needs of network processing which, although limited to specialized functionalities, are also flexible enough to keep up with often changing network protocols and architecture. Compared to general processors performing a variety of tasks, network processors primarily perform packet processing tasks using a relatively small amount of software code. Examples of specialized packet processing include packet routing, switching, forwarding, and bridging. Some network processors even have arrays of processing units with multithreading capability to process more packets at the same time. As network processors have taken on additional functionalities, however, what was once a specialized device responsible for a few tasks has matured into a general processing device responsible for numerous network processing tasks.
Consequentially, network processors are unable to perform application-level content inspection at high data rates. Application-level content inspection, or deep content inspection, involves regular expression matching of a byte stream in a data packet payload. An instruction set in a network processor is designed for general purpose network tasks, and not specifically for packet parsing. Thus, general purpose code used for parsing tasks is inefficient. Furthermore, content inspection is a computationally intensive task that dominates network processor bandwidth and other resources. In order to provide additional packet parsing functionality on the network processor, even more resources would need to be taken from other network processing tasks. Consequentially, current network processors are not suited for deep content inspection at high speeds.
Moreover, current processors that are dedicated to parsing packets lack flexibility for adaptability to new signatures and protocols. These processors are instead hard-wired to handle state of the art signatures and protocols known at production time. Software used for packet processing can adapt to changes, but does not perform at a high enough data rate.
Accordingly, there is a need for a robust packet processor that provides the flexibility and performance rate to perform content inspection concomitant with current and future networking demands. Furthermore, this solution should provide programmability to enhance traditional regular expression matching operations.